A New DFT Architecture to Reduce Test Data Volume and Test Application Time

Authors

  • Zhang Ling
  • Kuang Jishun School of Computer, Hubei Polytechnic University, Huangshi,
  • Mei Junjin

Keywords:

test data compression, integrated circuits, broadcast architecture, design for test

Abstract

This paper proposes a new DFT Architecture that contains three test scan modes. The test data could be interval broadcast to scan chains whenever the data in corresponding locations are compatible. Compared with the conventional broadcast scan architecture, the proposed architecture achieves better compression ratio in all cases, and the test application time is also induced. The hardware overhead is very low. Both theoretical and experimental results prove efficacy and versatility of the proposed scheme.

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Published

2016-09-12

Issue

Engineering Review, Vol. 36, No. 3

Section

Articles

License

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